CPU Design Logisim / SurprizingFacts

One of the chapters of the book "Code" (Author: Charles Petzold) is devoted to the design of the CPU and at the beginning of the chapter describes a device that allows you to sum sets of numbers stored in memory. We will design this scheme in Logisim. We take a set of eight-digit numbers and connect it to the multiplexer, the transition from one number to another will be performed using a counter connected to the select input of the multiplexer, and to the output of the multiplexer we connect the accumulator and the accumulator. We will use the button as the clock generator. Data will be loaded into the battery when the button is released (this is done using the NOT element connected to the button).

Then we implement the operation "subtraction", and we will store our operations (commands) in the hotel array. Command "0" performs addition, and commands "1" – subtraction. Further, these commands are fed to the input of the multiplexer connected to the Summator and the Subtractor.

Next, let's say we need to find three sums: three terms, two summands and two more terms. We implement a device that allows you to load a value from the memory into the battery and store the value from the battery in the memory, for this we remove the "subtractor" from the circuit, and the multiplexer we used to select the operation we will now use to retrieve the data from the memory.

In order to implement the "save" command, in the "data" array, replace the "Contact" elements with eight-bit registers, add a demultiplexer (decoder) for writing to the registers.

Increase the number of commands: command 10 loads the item from memory to the battery,
Command 00 adds a number from memory to the battery, command 01 stores the value from the battery in memory. "Splitter" allows you to separate the bits of the command, the lower bit to send to the multiplexer, the elder to the demultiplexer.

Let's replace separate registers with RAM arrays.

We will use a circuit with one synchronous read / write port (available by default). For the record, we will use the managed buffer.

In our device, the codes and data are stored in different memory blocks (Harvard architecture). We design a device in which the codes and data will be stored in one block (von Neumann architecture).

The first four digits of the eight-bit memory cell will store the command, the second four bits will store the address (absolute direct addressing).

We will load the address and command into separate registers, and then use the multiplexer to move to the saved address. To write data to RAM, we will use the delay circuit of the pulse delivery based on the shift register.

Command 3 loads the item from memory into the battery, command 2 adds the number from memory to the battery, command 4 writes the contents of the battery into RAM.

Here is an example of a program that adds three numbers (cells 8, 9, a) and stores the result in a free cell (cell b): 38 29 2a 4b.

Let's add also the possibility to make unconditional transitions.

We realize the device in which only one command will be executed – the command of unconditional transition. To do this, we will send the four lower digits (actually, the address) to the counter that generates the address, and we will send the command stored in the upper bits of the memory cell to the boot port.

For example, to jump to a cell with address 6, Team 1945.

Add this device to the main scheme.

In general, geektimes already had an article devoted to designing CPU in Logisim.

All the diagrams presented in the article can be downloaded in one file.

Logisim can be downloaded here